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SI5022/Si5023
PRELIMINARY DATA SHEET
MULTI-RATE SONET/SDH CDR IC
Features
WITH
LIMITING AMP
High Speed Clock and Data Recovery device with Integrated Limiting Amp:
! ! ! ! !
Supports OC-48/12/3, STM-16/4/1, Gigabit Ethernet, and 2.7 Gbps FEC DSPLLTM Technology Low Power--370 mW (TYP) Small Footprint: 5 mm x 5 mm Bit-Error-Rate Alarm
! ! ! ! ! !
External Reference Not Required Jitter Generation 3.0 mUIRMS(TYP) Loss-of-signal Level Alarm Data Slicing Level Control 10 mVPP Differential Sensitivity 2.5 V (SI5022) or 3.3 V (Si5023) Supply
Ordering Information: See page 14.
Applications
! !
SONET/SDH/ATM Routers Add/Drop Multiplexers ! Digital Cross Connects ! Gigabit Ethernet Interfaces
! !
SONET/SDH Test Equipment Optical Transceiver Modules ! SONET/SDH Regenerators ! Board Level Serial Links
Pin Assignments SI5022/23
BER_ALM CLKOUT+
23
The SI5022/23 is a fully integrated, high performance limiting amp and clock and data recovery (CDR) IC for high-speed serial communication systems. It extracts timing information and data from a serial input at OC-48/12/3, STM-16/4/1, or Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data streams is also provided for OC-48/STM-16 applications that employ forward error correction (FEC). An external reference clock is not required; applications with or without an external reference clock are supported. Silicon Laboratories' DSPLLTM technology eliminates sensitive noise entry points thus making the PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance. The SI5022/23 represents a new standard in low jitter, low power, small size, and integration for high speed LA/CDRs. It operates from either a 3.3 V (Si5023) or 2.5 V (SI5022) supply over the industrial temperature range (-40C to 85C).
28
27
26
VDD
Description
NC RATESEL0 RATESEL1 LOS_LVL SLICE_LVL REFCLK+ REFCLK- LOL
1 2 3 4 5 6 7 8
25
24
CLKOUT-
22 21 20 19
CLKDSBL
BER_LVL
VDD REXT RESET/CAL VDD DOUT+ DOUT- TDI
GND Pad
18 17 16 15
9
10
11
12
13
14
LOS
DSQLCH
DIN+
LTR
VDD
Top View
Functional Block Diagram
DSQLCH
Squelch C ontrol
R etim er
2
BU F
D O U T+ D O U T- CLKDSBL
D IN + D IN -
2
Lim iting AM P
D S P LLTM Phase-Locked Loop
2
BU F
C L K O U T+ C L K O U T- LO L
C ontrol
L O S _L V L
2
R E S E T /C AL
Bias G en
S L IC E _L V L LO S BER_LVL
LTR
R ATS E L [1:0]
REXT
REFCLK+ REFCLK- B E R _ AL M (Optional)
Preliminary Rev. 0.46 5/01
Copyright (c) 2001 by Silicon Laboratories
SI5022/23-DS046
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).
DIN-
VDD
S i5 02 2/ S i5 023
2
Preliminary Rev. 0.46
SI5022/Si5023 TA B L E O F CON T E N T S
Section Page
4 5 11 11 11 11 11 12 12 12 12 13 13 13 14 14 14 14 14 14 14 16 17 20 21 22
Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSPLLTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Without an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation With an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lock-to-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss-of-Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit-Error-Rate (BER) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET/DSPLL Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: SI5022/23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preliminary Rev. 0.46
3
S i5 02 2/ S i5 023
Detailed Block Diagram
LOS
B ER _LV L
B E R _A L M
LTR
R AT E S E L [0:1 ]
D SQ LC H
L O S _L V L
S ig n a l D e tec t
BER M o n ito r R e tim e D O U T+ D O U T-
D IN + L im itin g Am p D IN + n P h as e D e te cto r A/D DSP VCO CLK D ivid ers
C LK O U T+ C LK O U T-
CLK_DSBL S L IC E _L V L S lic in g C o n tro l
R E FC LK (o p tio n al)
Lock D e te c tio n LOL
REXT
B ia s G en era tio n
C a lib ra tio n
R E S E T /C AL
Figure 1. Detailed Block Diagram
4
Preliminary Rev. 0.46
SI5022/Si5023
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Ambient Temperature SI5022 Supply Voltage2 Si5023 Supply Voltage2 Symbol TA VDD VDD Test Condition Min1 -40 2.375 3.135 Typ 25 2.5 3.3 Max1 85 2.625 3.465 Unit C V V
Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25C unless otherwise stated. 2. The SI5022/23 specifications are guaranteed when using the recommended application circuit (including component tolerance) of Figure 5 on page 10.
V SIGNAL+ SIGNAL- V IS
t A. Operation with Single-Ended Inputs V SIGNAL+ SIGNAL- 0.5 V ID
(SIGNAL+) - (SIGNAL-)
V ID t
B. Operation with Differential Inputs and Outputs
Figure 2. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT)
Preliminary Rev. 0.46
5
S i5 02 2/ S i5 023
t Cf -D DOUT t C r-D
CLK OUT
Figure 3. Clock to Data Timing
DOUT, CLKOUT tF tR
80% 20%
Figure 4. DOUT and CLKOUT Rise/Fall Times
6
Preliminary Rev. 0.46
SI5022/Si5023
Table 2. DC Characteristics
(VDD=2.5 V 5% for SI5022 or 3.3 V 5% for Si5023, TA = -40C to 85C)
Parameter Supply Current OC-48 and FEC (2.7 GHz) GigE OC-12 OC-3 Power Dissipation OC-48 and FEC (2.7 GHz) GigE OC-12 OC-3 Power Dissipation OC-48 and FEC (2.7 GHz) GigE OC-12 OC-3 Common Mode Input Voltage (DIN)* Common Mode Input Voltage (REFCLK)* DIN Single-ended Input Voltage Swing* DIN Differential Input Voltage Swing* REFCLK Single-ended Input Voltage Swing* REFCLK Differential Input Voltage Swing* Input Impedance (DIN, REFCLK) Differential Output Voltage Swing (DOUT) Differential Output Voltage Swing (CLKOUT) Output Common Mode Voltage (DOUT,CLKOUT) Output Impedance (DOUT,CLKOUT) Output Current Short to GND (DOUT,CLKOUT) Output Current Short to VDD (DOUT,CLKOUT) Input Voltage Low (LVTTL Inputs) Input Voltage High (LVTTL Inputs) Input Low Current (LVTTL Inputs) Input High Current (LVTTL Inputs) Output Voltage Low (LVTTL Outputs) Output Voltage High (LVTTL Outputs) Input Impedance (LVTTL Inputs) PWRDN/CAL Leakage Current LOS_LVL, BER_LVL, SLICE_LVL Input Impedance
Symbol Test Condition IDD
Min -- -- -- --
Typ 148 150 152 154 370 375 380 385 488 495 502 508 1.50 2.00 -- -- -- -- 100 940 900 1.825 100 25 -15 -- -- -- -- -- -- -- 25 100
Max 160 162 164 165 400 405 410 414 554 561 568 572 1.58 2.10 500 1000 750 1500 116 TBD TBD TBD 116 TBD -- .8 -- 10 10 0.4 -- -- TBD TBD
Unit mA
PD
VDD = 2.5 V ( 5%)
-- -- -- -- -- -- -- -- 1.42 1.90 10 10 200 200 84 TBD TBD TBD 84 -- TBD -- 2.0 -- -- -- 2.0 10 TBD TBD
mW
PD
VDD = 3.3 V ( 5%)
mW
VICM VICM VIS VID VIS VID RIN VOD VOD VOCM ROUT ISC(-) ISC(+) VIL VIH IIL IIH VOL VOH RIN IPWRDN RIN
See Figure 11 See Figure 10 See Figure 2A See Figure 2B See Figure 2A See Figure 2B Line-to-Line 100 Load Line-to-Line 100 Load Line-to-Line 100 Load Line-to-Line Single-ended
V V mV mV mV mV mV (pk-pk) mV (pk-pk) V mA mA V V A A V V k A k
IO = 2 mA IO = 2 mA VPWRDN 0.8 V
*Note: These inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input must be ac coupled to ground.
Preliminary Rev. 0.46
7
S i5 02 2/ S i5 023
Table 3. AC Characteristics (Clock and Data)
(VDD=2.5 V 5% for SI5022 or 3.3 V 5% for Si5023, TA = -40C to 85C)
Parameter Output Clock Rate Output Rise Time Output Fall Time Clock to Data Delay FEC (2.7 GHz) OC-48 GigE OC-12 OC-3 Clock to Data Delay FEC (2.7 GHz) OC-48 Input Return Loss Slicing Level Offset*
(relative to the internally set input common mode voltage)
Symbol fCLK tR tF tCr-D
Test Condition Figure 4 Figure 4 Figure 3
Min .15 -- -- TBD TBD TBD TBD TBD
Typ -- 100 100 250 255 500 890 4100 TBD TBD -- -- --
Max 2.7 TBD TBD TBD TBD TBD TBD TBD TBD TBD -- -- 15
Unit GHz ps ps ps
tCf-D
Figure 3 TBD TBD 100 kHz-2.5 GHz 2.5 GHz-4.0 GHz TBD TBD -15 ps dB dB mV
VSLICE
SLICE_LVL = 750 mV to 2.25 V SLICE_LVL = 750 mV to 2.25 V
Slicing Level Accuracy
-500
--
500
V
*Note: Adjustment voltage (relative to the internally set input common mode voltage) is calculated as follows: VSLICE = (SLICE_LVL - 1.50 V)/50.
8
Preliminary Rev. 0.46
SI5022/Si5023
Table 4. AC Characteristics (PLL Characteristics)
(VDD=2.5 V 5% for SI5022 or 3.3 V 5% for Si5023, TA = -40C to 85C)
Parameter Jitter Tolerance (OC-48)*
Symbol JTOL(PP)
Test Condition f = 600 Hz f = 6000 Hz f = 100 kHz f = 1 MHz f = 30 Hz f = 300 Hz f = 25 kHz f = 250 kHz f = 30 Hz f = 300 Hz f = 6.5 kHz f = 65 kHz IEEE 802.3z Clause 38.68
Min 40 4 4 0.4 40 4 4 0.4 60 6 6 0.6 600
Typ TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Max -- -- -- -- -- -- -- -- -- -- -- -- --
Unit UIPP UIPP UIPP UIPP UIPP UIPP UIPP UIPP UIPP UIPP UIPP UIPP ps
Jitter Tolerance (OC-12 Mode)*
JTOL(PP)
Jitter Tolerance (OC-3 Mode)*
JTOL(PP)
Jitter Tolerance (Gigabit Ethernet) TJT(PP) Receive Data Total Jitter Tolerance IEEE 802.3z Clause 38.69 Jitter Tolerance (Gigabit Ethernet) DJT(PP) Receive Data Deterministic Jitter Tolerance JGEN(RMS) with no jitter on serial data RMS Jitter Generation* Peak-to-Peak Jitter Generation* Jitter Transfer Bandwidth* JGEN(PP) JBW with no jitter on serial data OC-48 Mode OC-12 Mode OC-3 Mode Jitter Transfer Peaking* Acquisition Time (Reference clock applied) JP TAQ After falling edge of PWRDN/CAL From the return of valid data After falling edge of PWRDN/CAL From the return of valid data
370
TBD
--
ps
-- -- -- -- -- -- 1.45 40 TBD TBD 19.44 -100 TBD
3.0 25 -- -- -- 0.03 1.5 60 TBD TBD -- -- 600
5.0 55 2.0 500 130 0.1 1.7 150 TBD TBD 168.75 100 TBD
mUI mUI MHz kHz kHz dB ms s ms ms MHz ppm ppm
Acquisition Time (Reference-less operation)
TAQ
Reference Clock Range Input Reference Clock Frequency Tolerance Frequency Difference at which Receive PLL goes out of Lock (REFCLK compared to the divided down VCO clock) Frequency Difference at which Receive PLL goes into Lock (REFCLK compared to the divided down VCO clock)
CTOL
TBD
300
TBD
ppm
*Note: As defined in Bellcore specifications: GR-253-CORE, Issue 2, December 1995. Using PRBS 223 - 1 data pattern.
Preliminary Rev. 0.46
9
S i5 02 2/ S i5 023
Table 5. Absolute Maximum Ratings
Parameter DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range Lead Temperature (soldering 10 seconds) ESD HBM Tolerance (100 pf, 1.5 k) TJCT TSTG Symbol VDD VDIG VDIF Value -0.5 to 2.8 (SI5022) -0.5 to 3.5 (Si5023) -0.3 to 3.6 -0.3 to (VDD+ 0.3) 50 -55 to 150 -55 to 150 300 1 Unit V V V mA C C C kV
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 6. Thermal Characteristics
Parameter Thermal Resistance Junction to Ambient Symbol JA Test Condition Still Air Value 38 Unit C/W
LVTTL Control Inputs
BER Alarm Loss-of-Signal Indicator Loss-of-Lock Indicator Indicator
2
RESET/CAL
CLKDSBL
RATESEL1-0
BER_ALM
LTR
DSQLCH
High Speed Serial Input
DIN+ DIN-
DOUT+ DOUT-
LOS
LOL
Recovered Data
SI5022/23
System Reference Clock (Optional) REFCLK+ REFCLK- CLKOUT+ CLKOUT- Recovered Clock
SLICE_LVL
LOS_LVL
BER_LVL
REXT
VDD
10 k
0.1 F 2200 pF 20 pF
Loss-of-Signal Level Set
Data Slice Level Set
Bit Error Rate Level Set
Figure 5. SI5022/23 Typical Application Circuit
10
Preliminary Rev. 0.46
GND
VDD
SI5022/Si5023
Functional Description
The SI5022/23 integrates a high-speed limiting amplifier (LA) with a multi-rate clock and data recovery unit (CDR) that operates up to 2.7 Gbps. No external reference clock is required for clock and data recovery. The limiting amplifier magnifies very low-level input data signals so that accurate clock and data recovery can be performed. The CDR uses Silicon Laboratories' DSPLL technology to recover a clock synchronous to the input data stream. The recovered clock is used to retime the incoming data, and both are output synchronously via current-mode logic (CML) drivers. Silicon Laboratories' DSPLL technology ensures superior jitter performance while eliminating the need for external loop filter components found in traditional phase-lock loop implementations. The limiting amplifier includes a control input for adjusting the 0/1 data slicing level and provides a lossof-signal level alarm output. The CDR includes a biterror-rate performance monitor which signals a high biterror-rate condition (associated with excessive incoming jitter) relative to an externally adjustable biterror-rate threshold. The optional reference clock minimizes the CDR acquisition time and provides a stable reference for maintaining the output clock when locking to reference is desired. This technology enables clock and data recovery with far less jitter than is generated using traditional methods and it eliminates performance degradation caused by external component aging. In addition, because external loop filter components are not required, sensitive noise entry points are eliminated, thus making the DSPLL less susceptible to board-level noise sources and making SONET/SDH jitter compliance easier to attain in the application.
Multi-Rate Operation
The SI5022/23 supports clock and data recovery for OC-48 and STM-16 data streams. In addition, the PLL was designed to operate at data rates up to 2.7 Gbps to support OC-48/STM-16 applications that employ forward error correction (FEC). Multi-rate operation is achieved by configuring the device to divide down the output of the VCO to the desired data rate. The divide factor is configured by the RATESEL[0:1] pins. The RATESEL[0:1] configuration and associated data rates are given in Table 7.
Table 7. Multi-Rate Configuration
RATESEL [0:1]
11 10 01 00
SONET/ SDH
2.488 Gbps 1.244 Gbps 622.08 Mbps 155.52 Mbps
Gigabit Ethernet
-- 1.25 Gbps -- --
Limiting Amplifier
The limiting amplifier accepts the low-level signal output from a transimpedance amplifier (TIA). The low-level signal is amplified to a usable level for the clock and data recovery unit. The minimum input swing requirement is specified in Table 2. Larger input amplitudes (up to the maximum input swing specified in Table 2) are accommodated without degradation of performance. The limiting amplifier ensures optimal data slicing by using a digital dc offset cancellation technique to remove any dc bias introduced by the amplification stage.
OC-48 with 15/14 FEC
2.67 Gbps -- -- --
CLK Divider
1 2 4 16
Operation Without an External Reference
The SI5022/23 can perform clock and data recovery without an external reference clock. Tying the REFCLK inputs to GND configures the device to operate without an external reference clock. Clock recovery is achieved by monitoring the timing quality of the incoming data relative to the VCO frequency. Lock is maintained by continuously monitoring the incoming data timing quality and adjusting the VCO accordingly. Details of the lock detection and the lock-to-reference functions while in this mode are described in their respective sections below.
Note: Without an external reference the acquisition of data is dependent solely on the data itself and will typically require more time to acquire lock than when a reference is applied.
DSPLLTM
The SI5022/23 PLL structure (shown in Figure 1 on page 4) utilizes Silicon Laboratories' DSPLL technology to maintain superior jitter performance while eliminating the need for external loop filter components found in traditional PLL implementations. This is achieved by using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in analog PLL designs. This algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage controlled oscillator (VCO).
Preliminary Rev. 0.46
11
S i5 02 2/ S i5 023
Operation With an External Reference
The SI5022/23 device's optional external reference clock centers the DSPLL, minimizes the acquisition time, and maintains a stable output clock (CLKOUT) when lock-to-reference (LTR) is asserted. When the reference clock is present, the SI5022/23 will use the reference clock to center the VCO output frequency so that clock and data can be recovered from the input data stream. The device will self configure for operation with one of three reference clock frequencies. This eliminates the need to externally configure the device to operate with a particular reference clock. The reference clock centers the VCO for a nominal output between 2.5 and 2.7 GHz. The VCO frequency is centered at 16, 32, or 128 times the reference clock frequency. Detection circuitry continuously monitors the reference clock input to determine whether the device should be configured for a reference clock that is 1/16, 1/32, or 1/128 the nominal VCO output. Approximate reference clock frequencies for some target applications are given in Table 8. output clock during out-of-lock conditions, the lock-toreference (LTR) input can be used to force the PLL to lock to the externally supplied reference. In the absence of an external reference, the lock detect circuitry uses a data quality measure to determine when frequency lock has been lost with the incoming data stream. Once LOL has been asserted, it will remain active until data is reacquired. During this reacquisition period, CLKOUT may vary by approximately 10% from the nominal data rate. For applications requiring a more stable output clock during out-of-lock conditions, LTR can be used to stabilize the output clock.
Lock-to-Reference
The lock-to-reference input (LTR) can be used to force a stable output clock when an alarm condition, like LOS, exists. In typical applications, the LOS output would be tied to the LTR input to force a stable output clock when the input data signal is lost. When LTR is asserted, the DSPLL is prevented from acquiring the data signal present on DIN. The operation of the LTR control input depends on which reference clocking mode is used. When an external reference clock is present, assertion of LTR will force the DSPLL to lock CLKOUT to the provided reference. If no external reference clock is used, LTR will force the DSPLL to hold the digital frequency control input to the VCO at the last value. This produces an output clock that is stable as long as supply and temperature are constant.
Table 8. Typical REFCLK Frequencies
SONET/SDH 19.44 MHz 77.76 MHz Gigabit Ethernet 19.53 MHz 78.125 MHz SONET/ SDH with 15/14 FEC 20.83 MHz 83.31 MHz Ratio of VCO to REFCLK 128 32 16
Loss-of-Signal
The SI5022/23 indicates a loss-of-signal condition on the LOS output pin when the input peak-to-peak signal level on DIN falls below an externally controlled threshold. The LOS threshold range is specified in Table 3 and is set by applying a voltage on the LOS_LVL pin. The graph in Figure 6 illustrates the LOS_LVL mapping to the LOS threshold. The LOS output is asserted when the input signal drops below the programmed peak-to-peak value.
155.52 MHz 156.25 MHz 166.63 MHz
Lock Detect
The SI5022/23 provides lock-detect circuitry that indicates whether the PLL has achieved frequency lock with the incoming data. The operation of the lockdetector depends on the reference clock option used. When an external reference clock is provided, the circuit compares the frequency of a divided down version of the recovered clock with the frequency of the supplied reference clock (REFCLK). If the recovered clock frequency deviates from that of the reference clock by the amount specified in Table 4 on page 9, the PLL is declared out of lock, and the loss-of-lock (LOL) pin is asserted. In this state, the DSPLL will periodically try to reacquire lock with the incoming data stream. During reacquisition, the recovered clock frequency (CLKOUT) will drift over a 1% range relative to the supplied reference clock. The LOL output will remain asserted until the recovered clock frequency is within the REFCLK frequency by the amount specified in Table 4 on page 9. In applications requiring a more stable
12
LOS Threshold (m V P P )
30 m V
LOS D isabled
15 m V
LOS Undefined
4 0 m V /V
0 mV 0V 1 .0 0 V 1 .5 0 V 1 .8 7 5 V 2 .2 5 V
L O S _L V L (V )
Figure 6. LOS_LVL Mapping
Preliminary Rev. 0.46
SI5022/Si5023
Approximately 6 dB of level detection hysteresis prevents unnecessary switching on LOS when marginal input data swing peak-to-peak levels are present. Hysteresis is defined as the difference between the LOS deassert level (LOSD) and the LOS assert level (LOSA). The hysteresis in decibels is calculated as 20log((LOSD - LOSA)/LOSA). The relationship between the LOS assert level and the LOS deassert level is shown in Figure 7. When the LOS assert level is set below 10 mV, the amount of hysteresis is fixed at 5 mV. When the LOS assert level is set above 10 mV, the amount of hysteresis is approximately 6 dB. common mode voltage) are supported. The 0/1 slicing level is set by applying a voltage between 0.75 V and 2.25 V to the SLICE_LVL input. The voltage present on SLICE_LVL maps to the 0/1 slicing level as follows:
( VSLICE_LVL - 1.5 V ) VSLICE = -----------------------------------------------------50
where VSLICE is the slicing level and VSLICE_LVL is the voltage applied to the SLICE_LVL pin. When SLICE_LVL is driven below 500 mV, the 0/1 slicing level adjustment is disabled, and the slicing level is set to the cross-point of the differential input signal.
PLL Performance
45 m V
LO S Deassert Level (m V PP )
The PLL implementation used in the SI5022/23 is fully compliant with the jitter specifications proposed for SONET/SDH equipment by Bellcore GR-253-CORE, Issue 2, December 1995 and ITU-T G.958. Jitter Tolerance The SI5022/23's tolerance to input jitter exceeds that of the Bellcore/ITU mask shown in Figure 8. This mask defines the level of peak-to-peak sinusoid jitter that must be tolerated when applied to the differential data input of the device.
Note: There are no entries in the mask table for the data rate corresponding to OC-24 as that rate is not specified by either GR-253 or G.958.
10 mV 30 mV
Sinusoidal Input Jitter (UI PP ) 15 1.5 0.15
15 m V 11 m V
6 mV
Slope = 20 dB/Decade
LO S A ssert L evel (m V P P )
Figure 7. Hysteresis Dependency
Bit-Error-Rate (BER) Detection
The SI5022/23 uses a proprietary Silicon Laboratories algorithm to generate a bit-error-rate (BER) alarm on the BER_ALM pin if the observed BER is greater than a user programmable threshold. Bit error detection relies on the input data edge timing; edges occurring outside of the expected event window are counted as bit errors. The BER alarm threshold can be set to one of 64 discrete values between 10-3 and 10-4. The BER threshold is programmed by applying a voltage to the BER_LVL pin between 500 mV and 2.25 V corresponding to 10-3 and 10-4 respectively.
f0
f1
f2 f3 Frequency
ft
SONET D ata R ate
F0 (H z)
F1 (H z)
F2 F3 (kH z) (kH z)
Ft (kH z)
OC-48 OC-12 OC-3
10 10 10
600 30 30
6000 300 300
100 25 6.5
1000 250 65
Figure 8. Jitter Tolerance Specification
Jitter Transfer The SI5022/23 exceeds all relevant Bellcore/ITU specifications related to SONET/SDH jitter transfer. Jitter transfer is defined as the ratio of output signal jitter to input signal jitter as a function of jitter frequency. (See Figure 9.) These measurements are made with an input
Data Slicing Level
The SI5022/23 provides the ability to externally adjust the 0/1 slicing level for applications that require biterror-rate (BER) optimization. Adjustments in slicing level of 15 mV (relative to the internally set input
Preliminary Rev. 0.46
13
S i5 02 2/ S i5 023
test signal that is degraded with sinusoidal jitter whose magnitude is defined by the mask in Figure 9.
Jitter Transfer
used to reduce power consumption in applications that do not use the recovered clock.
Data Squelch
The SI5022/23 provides a data squelching pin, DSQLCH, that is used to set the recovered data output, DOUT, to binary zero. When the DSQLCH pin is asserted, the DOUT logic signal is held at a binary zero. This pin can be is used to squelch corrupt data during LOS and LOL situations. Care must be taken when ac coupling these outputs; a long string of zeros will not be held through ac coupling capacitors.
0.1 dB
20 dB/Decade Slope Acceptable Range
Device Grounding
Fc Frequency
SONET D ata R ate
Fc (kH z)
OC-48 OC-12 OC-3
2000 500 130
The SI5022/23 uses the GND pad on the bottom of the 28-pin micro leaded package (MLP) for device ground. This pad should be connected directly to the analog supply ground. See Figures 13 and 14 for the ground (GND) pad location.
Bias Generation Circuitry
The SI5022/23 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents which significantly reduces power consumption versus traditional implementations that use an internal resistor. The bias generation circuitry requires a 10 k (1%) resistor connected between REXT and GND.
Figure 9. Jitter Transfer Specification
Jitter Generation The SI5022/23 exceeds all relevant specifications for jitter generation proposed for SONET/SDH equipment. The jitter generation specification defines the amount of jitter that may be present on the recovered clock and data outputs when a jitter free input signal is provided. The SI5022/23 typically generates less than 3.0 mUIRMS of jitter when presented with jitter-free input data.
Voltage Regulator
The SI5022 and Si5023 operate from different external supply voltages. Internally the devices are identical and operate from a 2.5 V supply. The SI5022 takes the 2.5 V supply directly from the external supply connections. The Si5023 regulates 2.5 V internally down from the external 3.3 V supply. Both devices consume 148 mA typically. In addition to supporting 3.3 V systems, the on-chip linear regulator offers better power supply noise rejection versus the direct 2.5 V supply.
RESET/DSPLL Calibration
The SI5022/23 achieves optimal jitter performance by using self-calibration circuitry to set the loop gain parameters within the DSPLL. For the self-calibration circuitry to operate correctly, the power supply voltage must exceed TBD V when calibration occurs. Selfcalibration is initiated by a high-to-low transition on the RESET/CAL pin. The RESET/CAL pin must be held high for at least 1 S after the supply has stabilized on power-up for optimum device operation. When RESET/ CAL is released (set to low) the digital logic resets to a known initial condition, recalibrates the DSPLL, and will begin to lock to the incoming data stream.
Differential Input Circuitry
The SI5022/23 provides differential inputs for both the high speed data (DIN) and the reference clock (REFCLK) inputs. An example termination for these inputs is shown in Figure 10 and Figure 11 respectively. In applications where direct dc coupling is possible, the 0.1 F capacitors may be omitted. (LOS operation is only guaranteed when ac coupled.) The data input limiting amplifier requires an input signal with a differential peak-to-peak voltage as specified in Table 2 to ensure a BER of at least 10-12. The REFCLK input differential peak-to-peak voltage requirement is specified in Table 2.
Clock Disable
The SI5022/23 provides a clock disable pin, CLK_DSBL, that is used to disable the recovered clock output, CLKOUT. When the CLK_DSBL pin is asserted, the positive and negative terminals of CLKOUT are tied to VDD through 100 on-chip resistors. This feature is
14
Preliminary Rev. 0.46
SI5022/Si5023
SI5022/23 Clock source
2.5 k 0.1 F Zo = 50 RFCLK + 10 k 0.1 F Zo = 50 2.5 k 102
2.5 V (5% )
RFCLK - 10 k
GND
Figure 10. Input Termination for REFCLK (AC Coupled)
T IA S i5 0 2 2 /2 3 2 .5 V ( 5 % )
0 .1 F Zo = 50
D IN + ,
50
5 k
50 0 .1 F Zo = 50 D IN - ,
7 .5 k
GND
Figure 11. Input Termination for DIN (AC Coupled)
Preliminary Rev. 0.46
15
S i5 02 2/ S i5 023
Differential Output Circuitry
The SI5022/23 utilizes a current-mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with ac coupling is shown in Figure 12. In applications in which direct dc coupling is possible, the 0.1 F capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is specified in Table 2.
SI5022/23 2.5 V (5% )
100
VDD
50
DOUT+, CLKOUT+
0.1 F
Zo = 50
DOUT-, CLKOUT-
0.1 F
Zo = 50
100
2.5 V (5% )
50
VDD
Figure 12. Output Termination for DOUT and CLKOUT (AC Coupled)
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Preliminary Rev. 0.46
SI5022/Si5023
Pin Descriptions: SI5022/23
BER_ALM CLKOUT+
23
CLKDSBL
28
27
26
25
24
RATESEL0 RATESEL1 LOS_LVL SLICE_LVL REFCLK+ REFCLKLOL
CLKOUT22 21 20 19
BER_LVL
VDD
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
VDD REXT RESET/CAL VDD DOUT+ DOUTTDI
GND Pad
18 17 16 15
LOS
DSQLCH
DIN+
LTR
VDD
Top View
Figure 13. SI5022/23 Pin Configuration Table 9. SI5022/23 Pin Descriptions
Pin # 1,2 Pin Name RATESEL0, RATESEL1 I/O I Signal Level LVTTL Data Rate Select. These pins configure the onboard PLL for clock and data recovery at one of four user selectable data rates. See Table 7 for configuration settings.
Note: These inputs have weak internal pull-ups.
VDD
DIN-
Description
3
LOS_LVL
I
LOS Level Control. The LOS threshold is set by the input voltage level applied to this pin. Figure 6 on page 12 shows the input setting to output threshold mapping. LOS is disabled when the voltage applied is less than 500 mV.
4
SLICE_LVL
I
Slicing Level Control. The slicing threshold level is set by applying a voltage to this pin as described in the Slicing Level section of the data sheet. If this pin is tied to GND, slicing level adjustment is disabled, and the slicing level is set to the midpoint of the differential input signal on DIN. Slicing level becomes active when the voltage applied to the pin is greater than 500 mV.
5,6
REFCLK+, REFCLK-
I
See Table 2
Differential Reference Clock (Optional). When present, the reference clock sets the center operating frequency of the DSPLL for clock and data recovery. Tie these pins to ground to configures the DSPLL to operate without an external reference clock. See Table 8 for typical reference clock frequencies.
Preliminary Rev. 0.46
17
S i5 02 2/ S i5 023
Table 9. SI5022/23 Pin Descriptions (Continued)
Pin # 7 Pin Name LOL I/O O Signal Level LVTTL Loss-of-Lock. This output is driven low when the recovered clock frequency deviates from the reference clock by the amount specified in Table 4 on page 9. If no external reference is supplied, this signal will be active when the internal PLL is no longer locked to the incoming data. 8 LTR I LVTTL Lock-to-Reference. When this pin is low, the DSPLL will disregard the data inputs. If an external reference is supplied, the output clock will be locked to the supplied reference. If no external reference is used, the DSPLL will lock the control loop until LTR is released.
Note: This input has a weak internal pull-up.
Description
9
LOS
O
LVTTL
Loss-of-Signal. This output pin is driven low when the input signal is below the threshold set via LOS_LVL. The LOS state will nominally have 3 dB of hysteresis relative to the level set on LOS_LVL. (LOS operation is guaranteed only when ac coupling is used on the clock input.)
10
DSQLCH
LVTTL
Data Squelch. When driven high, this pin forces the data present on DOUT to zero. For normal operation, this pin should be low. DSQLCH can be used during LOS/ LOL conditions to prevent random data from being presented to the system.
Note: This input has a weak internal pull-down.
11,14,18,21, 25 12,13
VDD DIN+, DIN- I
2.5 V or 3.3 V See Table 2
Supply Voltage. Nominally 2.5 V for SI5022 and 3.3 V for Si5023. Differential Data Input. Clock and data are recovered from the differential signal present on these pins. ac coupling is recommended.
15
TDI
I
LVTTL
Production Test Input. This pin is used during production testing and must be tied to GND for normal operation.
16,17
DOUT+, DOUT-
O
CML
Differential Data Output. The data output signal is a retimed version of the data recovered from the signal present on DIN. It is phase aligned with CLKOUT and is updated on the rising edge of CLKOUT.
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Preliminary Rev. 0.46
SI5022/Si5023
Table 9. SI5022/23 Pin Descriptions (Continued)
Pin # 19 Pin Name RESET/CAL I/O I Signal Level LVTTL Reset/Calibrate. Driving this input high for at least 1 S will reset internal device circuitry. A high to low transition on this pin will force a DSPLL calibration. For normal operation, drive this pin low. This pin should be used to force a DSPLL calibration on power-up to ensure optimal jitter performance.
Note: This input has a weak internal pull-down.
Description
20
REXT
External Bias Resistor. This resistor is used to establish internal bias currents within the device. This pin must be connected to GND through a 10 k (1%) resistor.
22,23
CLKOUT-, CLKOUT+
O
CML
Differential Clock Output. The output clock is recovered from the data signal present on DIN except when LTR is asserted or the LOL state has been entered.
24
CLKDSBL
I
LVTTL
Clock Disable. When this input is high, the CLKOUT output drivers are disabled. For normal operation, this pin should be low.
Note: This input has a weak internal pull-down.
26
BER_LVL
I
Bit Error Rate Level Control. The BER threshold level is set by applying a voltage to this pin. The applied voltage is mapped to one of 64 BER threshold levels. When the BER exceeds the programmed threshold, BER_ALM is driven low. If this pin is tied to GND, BER_ALM is disabled. If it is tied to VDD, BER_LVL defaults to 10-3 BER
27
BER_ALM
O
LVTTL
Bit Error Rate Alarm. This pin will be driven low to indicate that the BER threshold set by BER_LVL has been exceeded. The alarm will clear after the BER rate has improved by approximately a factor of 2.
28 GND Pad
NC GND GND
No Connect. Leave this pin unconnected. Supply Ground. Nominally 0.0 V. The GND pad found on the bottom of the 28-lead micro leaded package (see Figure 14) must be connected directly to supply ground. Minimize the ground path inductance for optimal performance.
Preliminary Rev. 0.46
19
S i5 02 2/ S i5 023
Ordering Guide
Table 10. Ordering Guide Part Number SI5022-BM Si5023-BM Package 28-lead MLP 28-lead MLP Voltage 2.5 3.3 Temperature -40C to 85C -40C to 85C
20
Preliminary Rev. 0.46
SI5022/Si5023
Package Outline
Figure 14 illustrates the package details for the SI5022 and Si5023. Table 11 lists the values for the dimensions shown in the illustration.
A D D /2 D1 D 1/2 N A A1 N b
1 2 3
E1/2
E/2
1 2 3 E (N d-1) Xe R EF.
E1
L
TOP V IEW
e (N d-1) Xe R EF. CC
C L
C L
b
A1
BOTTOM V IEW
SECTION "C-C"
SC ALE: N ON E e e
FOR ODD TERMINA L/SIDE
FOR EV EN TERMINA L/SIDE
Figure 14. 28-Lead Micro Leaded Package (MLP) Table 11. Package Diagram Dimensions Controlling Dimension: mm Symbol Millimeters Min Nom A -- 0.90 A1 0.00 0.01 b 0.18 0.23 D 5.00 BSC D1 4.75 BSC E 5.00 BSC E1 4.75 BSC N 28 Nd 7 Ne 7 e 0.50 BSC L 0.50 0.60
Max 1.00 0.05 0.30
0.75
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Preliminary Rev. 0.46
21
S i5 02 2/ S i5 023
Contact Information
Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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Preliminary Rev. 0.46

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